The present disclosure relates generally to semiconductor manufacturing and, more particularly, to a tapered profile via and method of fabricating a via including a tapered profile. The tapered profile via is a though-substrate via (also known as a through-silicon via (TSV) or through-wafer via).
Vias have been routinely used in semiconductor fabrication to provide electrical coupling between one or more layers of conductive material within a semiconductor device. More recently, through-silicon vias (TSV) have arisen as a method of overcoming limitations of conventional wire bonding for example, as performance and density requirements increase no longer allowing traditional wire bonding to be adequate. TSV allow for shorter interconnects by forming an interconnect in the z-axis. The interconnect is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate. TSV are also useful in forming interconnects for stacked wafers, stacked die, and/or combinations thereof.
The use of TSV technology however creates challenges. The aspect ratio of the via may be quite high (e.g. the thickness of the substrate or the depth of the via is large as compared to the diameter of the via). In conventional processes, the via also has a profile having substantially straight sidewalls. Such a high aspect ratio and straight wall profile and can lead to issues associated with filling (e.g. by depositing or plating) the via with material. For example, issues include poor sidewall coverage, improper seed or barrier layer formation, and/or voids in the metallization fill. Furthermore, conventional methods of forming a via may lead to an undesirable undercut in layers (e.g. undercuts between oxide and silicon) of the substrate.
As such, an improved via and method of fabricating such is desired.